/******************************************************************************
* Copyright (c) 2022 Xilinx, Inc.  All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

/*****************************************************************************/
/**
*
* @file psmx_local.h
*
* This file contains PSMX local registers information
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who  Date        Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00  sr   03/03/2022 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/

#ifndef XPSMFW_PSMX_LOCAL_H_
#define XPSMFW_PSMX_LOCAL_H_


#ifdef __cplusplus
extern "C" {
#endif

/**
 * PSMX_LOCAL_REG Base Address
 */
#define PSMX_LOCAL_REG_BASEADDR      (u32)0xEBC88000

/**
 * Register: PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000000 )
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU0_CORE0_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000004 )
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU0_CORE0_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE0_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000008 )
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU0_CORE1_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000000C )
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU0_CORE1_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE1_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000010 )
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU0_CORE2_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000014 )
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU0_CORE2_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE2_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000018 )
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU0_CORE3_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000001C )
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU0_CORE3_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU0_CORE3_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000020 )
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU1_CORE0_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000024 )
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU1_CORE0_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE0_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000028 )
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU1_CORE1_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000002C )
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU1_CORE1_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE1_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000030 )
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU1_CORE2_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000034 )
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU1_CORE2_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE2_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000038 )
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU1_CORE3_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000003C )
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU1_CORE3_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU1_CORE3_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000040 )
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU2_CORE0_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000044 )
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU2_CORE0_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE0_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000048 )
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU2_CORE1_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000004C )
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU2_CORE1_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE1_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000050 )
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU2_CORE2_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000054 )
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU2_CORE2_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE2_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000058 )
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU2_CORE3_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000005C )
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU2_CORE3_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU2_CORE3_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000060 )
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU3_CORE0_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000064 )
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU3_CORE0_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE0_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000068 )
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU3_CORE1_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000006C )
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU3_CORE1_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE1_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000070 )
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU3_CORE2_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000074 )
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU3_CORE2_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE2_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000078 )
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU3_CORE3_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000007C )
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_APU3_CORE3_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_APU3_CORE3_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000100 )
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_RPU_A_CORE0_PWR_STATUS
 */
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000104 )
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_A_CORE0_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000108 )
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_RPU_A_CORE1_PWR_STATUS
 */
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000010C )
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_A_CORE1_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000110 )
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_RPU_B_CORE0_PWR_STATUS
 */
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000114 )
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_B_CORE0_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000118 )
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_FULLRWMASK  (u32)0x0000001f
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_ISOLATION_SHIFT   4
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_ISOLATION_WIDTH   1
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_ISOLATION_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_ISOLATION_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_CNTRL_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_RPU_B_CORE1_PWR_STATUS
 */
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000011C )
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_STATUS_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_STATUS_PWR_GATES_SHIFT   0
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_STATUS_PWR_GATES_WIDTH   4
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_STATUS_PWR_GATES_MASK    (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_B_CORE1_PWR_STATUS_PWR_GATES_DEFVAL  (u32)0xf

/**
 * Register: PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000150 )
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_FULLRWMASK  (u32)0x000001ff
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_CNTRL_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL
 */
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000154 )
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_FULLRWMASK  (u32)0x000001ff
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU0_DSU_L3_CE_CNTRL_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000158 )
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU0_DSU_L3_PWR_STATUS_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000015C )
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_FULLRWMASK  (u32)0x000001ff
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_CNTRL_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL
 */
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000160 )
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_FULLRWMASK  (u32)0x000001ff
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU1_DSU_L3_CE_CNTRL_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000164 )
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU1_DSU_L3_PWR_STATUS_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000168 )
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_FULLRWMASK  (u32)0x000001ff
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_CNTRL_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL
 */
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000016C )
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_FULLRWMASK  (u32)0x000001ff
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU2_DSU_L3_CE_CNTRL_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000170 )
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU2_DSU_L3_PWR_STATUS_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000174 )
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_FULLRWMASK  (u32)0x000001ff
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_CNTRL_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL
 */
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000178 )
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_FULLRWMASK  (u32)0x000001ff
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU3_DSU_L3_CE_CNTRL_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS
 */
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000017C )
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_FULLMASK     (u32)0x000001ff
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_DEFVAL   (u32)0x1ff

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_LTDB_SHIFT   8
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_LTDB_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_LTDB_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_LTDB_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_SF_SHIFT   7
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_SF_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_SF_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_SF_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_VICTIM_SHIFT   6
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_VICTIM_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_VICTIM_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_VICTIM_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_DATA1_SHIFT   5
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_DATA1_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_DATA1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_DATA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_DATA0_SHIFT   4
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_DATA0_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_DATA0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_DATA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG3_SHIFT   3
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG3_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG2_SHIFT   2
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG2_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG1_SHIFT   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG1_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG0_SHIFT   0
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG0_WIDTH   1
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_APU3_DSU_L3_PWR_STATUS_TAG0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000200 )
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_FULLRWMASK  (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_B1_SHIFT   3
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_B1_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_B1_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_B1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_B0_SHIFT   2
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_B0_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_B0_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_B0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_A1_SHIFT   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_A1_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_A1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_A1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_A0_SHIFT   0
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_A0_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_A0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_CNTRL_A0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL
 */
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000204 )
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_FULLRWMASK  (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_DEFVAL   (u32)0xf

#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_B1_SHIFT   3
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_B1_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_B1_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_B1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_B0_SHIFT   2
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_B0_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_B0_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_B0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_A1_SHIFT   1
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_A1_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_A1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_A1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_A0_SHIFT   0
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_A0_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_A0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_RPU_CACHE_CE_CNTRL_A0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS
 */
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000208 )
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_FULLMASK     (u32)0x0000000f
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_B1_SHIFT   3
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_B1_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_B1_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_B1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_B0_SHIFT   2
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_B0_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_B0_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_B0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_A1_SHIFT   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_A1_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_A1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_A1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_A0_SHIFT   0
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_A0_WIDTH   1
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_A0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_RPU_CACHE_PWR_STATUS_A0_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_OCM_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000250 )
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_FULLMASK     (u32)0x00000f0f
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_FULLRWMASK  (u32)0x00000f0f
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_DEFVAL   (u32)0xf0f

#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I3_SHIFT   11
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I3_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I3_MASK    (u32)0x00000800
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I2_SHIFT   10
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I2_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I2_MASK    (u32)0x00000400
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I1_SHIFT   9
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I1_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I1_MASK    (u32)0x00000200
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I0_SHIFT   8
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I0_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I0_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B1_I0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I3_SHIFT   3
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I3_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I2_SHIFT   2
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I2_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I1_SHIFT   1
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I1_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I0_SHIFT   0
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I0_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_OCM_PWR_CNTRL_B0_I0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_OCM_RET_CNTRL
 */
#define PSMX_LOCAL_REG_OCM_RET_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000254 )
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_FULLMASK     (u32)0x00000f0f
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_FULLRWMASK  (u32)0x00000f0f
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I3_SHIFT   11
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I3_WIDTH   1
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I3_MASK    (u32)0x00000800
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I3_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I2_SHIFT   10
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I2_WIDTH   1
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I2_MASK    (u32)0x00000400
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I2_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I1_SHIFT   9
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I1_WIDTH   1
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I1_MASK    (u32)0x00000200
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I0_SHIFT   8
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I0_WIDTH   1
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I0_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B1_I0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I3_SHIFT   3
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I3_WIDTH   1
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I3_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I2_SHIFT   2
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I2_WIDTH   1
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I2_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I1_SHIFT   1
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I1_WIDTH   1
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I0_SHIFT   0
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I0_WIDTH   1
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_OCM_RET_CNTRL_B0_I0_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_OCM_CE_CNTRL
 */
#define PSMX_LOCAL_REG_OCM_CE_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000258 )
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_FULLMASK     (u32)0x00000f0f
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_FULLRWMASK  (u32)0x00000f0f
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_DEFVAL   (u32)0xf0f

#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I3_SHIFT   11
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I3_WIDTH   1
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I3_MASK    (u32)0x00000800
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I2_SHIFT   10
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I2_WIDTH   1
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I2_MASK    (u32)0x00000400
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I1_SHIFT   9
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I1_WIDTH   1
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I1_MASK    (u32)0x00000200
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I0_SHIFT   8
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I0_WIDTH   1
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I0_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B1_I0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I3_SHIFT   3
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I3_WIDTH   1
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I2_SHIFT   2
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I2_WIDTH   1
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I1_SHIFT   1
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I1_WIDTH   1
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I0_SHIFT   0
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I0_WIDTH   1
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_OCM_CE_CNTRL_B0_I0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_OCM_PWR_STATUS
 */
#define PSMX_LOCAL_REG_OCM_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000025C )
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_FULLMASK     (u32)0x00000f0f
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_DEFVAL   (u32)0xf0f

#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I3_SHIFT   11
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I3_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I3_MASK    (u32)0x00000800
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I2_SHIFT   10
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I2_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I2_MASK    (u32)0x00000400
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I1_SHIFT   9
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I1_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I1_MASK    (u32)0x00000200
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I0_SHIFT   8
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I0_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I0_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B1_I0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I3_SHIFT   3
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I3_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I2_SHIFT   2
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I2_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I1_SHIFT   1
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I1_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I0_SHIFT   0
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I0_WIDTH   1
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_OCM_PWR_STATUS_B0_I0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_TCM_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000300 )
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_FULLMASK     (u32)0x01010101
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_FULLRWMASK  (u32)0x01010101
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_DEFVAL   (u32)0x1010101

#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMB1_SHIFT   24
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMB1_WIDTH   1
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMB1_MASK    (u32)0x01000000
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMB1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMB0_SHIFT   16
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMB0_WIDTH   1
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMB0_MASK    (u32)0x00010000
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMB0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMA1_SHIFT   8
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMA1_WIDTH   1
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMA1_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMA0_SHIFT   0
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMA0_WIDTH   1
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMA0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_TCM_PWR_CNTRL_TCMA0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_TCM_RET_CNTRL
 */
#define PSMX_LOCAL_REG_TCM_RET_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000304 )
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_FULLMASK     (u32)0x01010101
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_FULLRWMASK  (u32)0x01010101
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMB1_SHIFT   24
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMB1_WIDTH   1
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMB1_MASK    (u32)0x01000000
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMB1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMB0_SHIFT   16
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMB0_WIDTH   1
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMB0_MASK    (u32)0x00010000
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMB0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMA1_SHIFT   8
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMA1_WIDTH   1
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMA1_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMA1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMA0_SHIFT   0
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMA0_WIDTH   1
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMA0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_TCM_RET_CNTRL_TCMA0_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_TCM_CE_CNTRL
 */
#define PSMX_LOCAL_REG_TCM_CE_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000308 )
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_FULLMASK     (u32)0x01010101
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_FULLRWMASK  (u32)0x01010101
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_DEFVAL   (u32)0x1010101

#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMB1_SHIFT   24
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMB1_WIDTH   1
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMB1_MASK    (u32)0x01000000
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMB1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMB0_SHIFT   16
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMB0_WIDTH   1
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMB0_MASK    (u32)0x00010000
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMB0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMA1_SHIFT   8
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMA1_WIDTH   1
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMA1_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMA0_SHIFT   0
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMA0_WIDTH   1
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMA0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_TCM_CE_CNTRL_TCMA0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_TCM_PWR_STATUS
 */
#define PSMX_LOCAL_REG_TCM_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000030C )
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_FULLMASK     (u32)0x01010101
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMB1_SHIFT   24
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMB1_WIDTH   1
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMB1_MASK    (u32)0x01000000
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMB1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMB0_SHIFT   16
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMB0_WIDTH   1
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMB0_MASK    (u32)0x00010000
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMB0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMA1_SHIFT   8
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMA1_WIDTH   1
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMA1_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMA1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMA0_SHIFT   0
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMA0_WIDTH   1
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMA0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_TCM_PWR_STATUS_TCMA0_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_GEM_PWR_CNTRL
 */
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000350 )
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_FULLMASK     (u32)0x00000101
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_FULLRWMASK  (u32)0x00000101
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_DEFVAL   (u32)0x101

#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_GEM1_SHIFT   8
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_GEM1_WIDTH   1
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_GEM1_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_GEM1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_GEM0_SHIFT   0
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_GEM0_WIDTH   1
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_GEM0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_GEM_PWR_CNTRL_GEM0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_GEM_CE_CNTRL
 */
#define PSMX_LOCAL_REG_GEM_CE_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000354 )
#define PSMX_LOCAL_REG_GEM_CE_CNTRL_FULLMASK     (u32)0x00000003
#define PSMX_LOCAL_REG_GEM_CE_CNTRL_FULLRWMASK  (u32)0x00000003
#define PSMX_LOCAL_REG_GEM_CE_CNTRL_DEFVAL   (u32)0x3

#define PSMX_LOCAL_REG_GEM_CE_CNTRL_GEM1_SHIFT   1
#define PSMX_LOCAL_REG_GEM_CE_CNTRL_GEM1_WIDTH   1
#define PSMX_LOCAL_REG_GEM_CE_CNTRL_GEM1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_GEM_CE_CNTRL_GEM1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_GEM_CE_CNTRL_GEM0_SHIFT   0
#define PSMX_LOCAL_REG_GEM_CE_CNTRL_GEM0_WIDTH   1
#define PSMX_LOCAL_REG_GEM_CE_CNTRL_GEM0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_GEM_CE_CNTRL_GEM0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_GEM_PWR_STATUS
 */
#define PSMX_LOCAL_REG_GEM_PWR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000358 )
#define PSMX_LOCAL_REG_GEM_PWR_STATUS_FULLMASK     (u32)0x00000101
#define PSMX_LOCAL_REG_GEM_PWR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_GEM_PWR_STATUS_DEFVAL   (u32)0x101

#define PSMX_LOCAL_REG_GEM_PWR_STATUS_GEM1_SHIFT   8
#define PSMX_LOCAL_REG_GEM_PWR_STATUS_GEM1_WIDTH   1
#define PSMX_LOCAL_REG_GEM_PWR_STATUS_GEM1_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_GEM_PWR_STATUS_GEM1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_GEM_PWR_STATUS_GEM0_SHIFT   0
#define PSMX_LOCAL_REG_GEM_PWR_STATUS_GEM0_WIDTH   1
#define PSMX_LOCAL_REG_GEM_PWR_STATUS_GEM0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_GEM_PWR_STATUS_GEM0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL
 */
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000400 )
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FULLMASK     (u32)0x0000003f
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FULLRWMASK  (u32)0x0000003f
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_DEFVAL   (u32)0x7f

#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FPD_CPM5_DFX_SHIFT   5
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FPD_CPM5_DFX_WIDTH   1
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FPD_CPM5_DFX_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FPD_CPM5_DFX_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FPD_CPM5_SHIFT   4
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FPD_CPM5_WIDTH   1
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FPD_CPM5_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_FPD_CPM5_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_OCM2_DFX_SHIFT   3
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_OCM2_DFX_WIDTH   1
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_OCM2_DFX_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_OCM2_DFX_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_OCM2_SHIFT   2
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_OCM2_WIDTH   1
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_OCM2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_OCM2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_FPD_DFX_SHIFT   1
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_FPD_DFX_WIDTH   1
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_FPD_DFX_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_FPD_DFX_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_FPD_SHIFT   0
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_FPD_WIDTH   1
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_FPD_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_DOMAIN_ISO_CNTRL_LPD_FPD_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_LOC_PWR_STATE0
 */
#define PSMX_LOCAL_REG_LOC_PWR_STATE0    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000410 )
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_DEFVAL   (u32)0xffffffff

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I3_SHIFT   31
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I3_MASK    (u32)0x80000000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I2_SHIFT   30
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I2_MASK    (u32)0x40000000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I1_SHIFT   29
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I1_MASK    (u32)0x20000000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I0_SHIFT   28
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I0_MASK    (u32)0x10000000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B1_I0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I3_SHIFT   27
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I3_MASK    (u32)0x08000000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I2_SHIFT   26
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I2_MASK    (u32)0x04000000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I1_SHIFT   25
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I1_MASK    (u32)0x02000000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I0_SHIFT   24
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I0_MASK    (u32)0x01000000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_OCM_B0_I0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMB1_SHIFT   23
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMB1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMB1_MASK    (u32)0x00800000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMB1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMB0_SHIFT   22
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMB0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMB0_MASK    (u32)0x00400000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMB0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMA1_SHIFT   21
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMA1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMA1_MASK    (u32)0x00200000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMA1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMA0_SHIFT   20
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMA0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMA0_MASK    (u32)0x00100000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_TCMA0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_B_CORE1_SHIFT   19
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_B_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_B_CORE1_MASK    (u32)0x00080000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_B_CORE1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_B_CORE0_SHIFT   18
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_B_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_B_CORE0_MASK    (u32)0x00040000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_B_CORE0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_A_CORE1_SHIFT   17
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_A_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_A_CORE1_MASK    (u32)0x00020000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_A_CORE1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_A_CORE0_SHIFT   16
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_A_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_A_CORE0_MASK    (u32)0x00010000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_RPU_A_CORE0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE3_SHIFT   15
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE3_MASK    (u32)0x00008000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE2_SHIFT   14
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE2_MASK    (u32)0x00004000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE1_SHIFT   13
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE1_MASK    (u32)0x00002000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE0_SHIFT   12
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE0_MASK    (u32)0x00001000
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU3_CORE0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE3_SHIFT   11
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE3_MASK    (u32)0x00000800
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE2_SHIFT   10
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE2_MASK    (u32)0x00000400
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE1_SHIFT   9
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE1_MASK    (u32)0x00000200
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE0_SHIFT   8
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE0_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU2_CORE0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE3_SHIFT   7
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE3_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE2_SHIFT   6
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE2_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE1_SHIFT   5
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE0_SHIFT   4
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU1_CORE0_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE3_SHIFT   3
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE3_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE2_SHIFT   2
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE2_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE1_SHIFT   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE0_SHIFT   0
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_LOC_PWR_STATE0_APU0_CORE0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_LOC_PWR_STATE1
 */
#define PSMX_LOCAL_REG_LOC_PWR_STATE1    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000414 )
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_FULLMASK     (u32)0x00000007
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_FULLRWMASK  (u32)0x00000007
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_DEFVAL   (u32)0x7

#define PSMX_LOCAL_REG_LOC_PWR_STATE1_FP_SHIFT   2
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_FP_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_FP_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_FP_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE1_GEM1_SHIFT   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_GEM1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_GEM1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_GEM1_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_LOC_PWR_STATE1_GEM0_SHIFT   0
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_GEM0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_GEM0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_LOC_PWR_STATE1_GEM0_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_LOC_AUX_PWR_STATE
 */
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000420 )
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I3_SHIFT   31
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I3_MASK    (u32)0x80000000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I3_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I2_SHIFT   30
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I2_MASK    (u32)0x40000000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I2_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I1_SHIFT   29
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I1_MASK    (u32)0x20000000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I0_SHIFT   28
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I0_MASK    (u32)0x10000000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B1_I0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I3_SHIFT   27
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I3_MASK    (u32)0x08000000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I3_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I2_SHIFT   26
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I2_MASK    (u32)0x04000000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I2_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I1_SHIFT   25
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I1_MASK    (u32)0x02000000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I0_SHIFT   24
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I0_MASK    (u32)0x01000000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_OCM_B0_I0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMB1_SHIFT   23
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMB1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMB1_MASK    (u32)0x00800000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMB1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMB0_SHIFT   22
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMB0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMB0_MASK    (u32)0x00400000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMB0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMA1_SHIFT   21
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMA1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMA1_MASK    (u32)0x00200000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMA1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMA0_SHIFT   20
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMA0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMA0_MASK    (u32)0x00100000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_TCMA0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_B_CORE1_SHIFT   19
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_B_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_B_CORE1_MASK    (u32)0x00080000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_B_CORE1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_B_CORE0_SHIFT   18
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_B_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_B_CORE0_MASK    (u32)0x00040000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_B_CORE0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_A_CORE1_SHIFT   17
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_A_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_A_CORE1_MASK    (u32)0x00020000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_A_CORE1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_A_CORE0_SHIFT   16
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_A_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_A_CORE0_MASK    (u32)0x00010000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_RPU_A_CORE0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE3_SHIFT   15
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE3_MASK    (u32)0x00008000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE3_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE2_SHIFT   14
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE2_MASK    (u32)0x00004000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE2_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE1_SHIFT   13
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE1_MASK    (u32)0x00002000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE0_SHIFT   12
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE0_MASK    (u32)0x00001000
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU3_CORE0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE3_SHIFT   11
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE3_MASK    (u32)0x00000800
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE3_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE2_SHIFT   10
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE2_MASK    (u32)0x00000400
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE2_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE1_SHIFT   9
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE1_MASK    (u32)0x00000200
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE0_SHIFT   8
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE0_MASK    (u32)0x00000100
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU2_CORE0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE3_SHIFT   7
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE3_MASK    (u32)0x00000080
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE3_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE2_SHIFT   6
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE2_MASK    (u32)0x00000040
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE2_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE1_SHIFT   5
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE1_MASK    (u32)0x00000020
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE0_SHIFT   4
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE0_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU1_CORE0_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE3_SHIFT   3
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE3_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE3_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE3_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE2_SHIFT   2
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE2_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE2_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE2_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE1_SHIFT   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE1_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE1_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE1_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE0_SHIFT   0
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE0_WIDTH   1
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE0_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_LOC_AUX_PWR_STATE_APU0_CORE0_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_LOCAL_GEN_STORAGE0
 */
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE0    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000430 )
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE0_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE0_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE0_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE0_DATA_SHIFT   0
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE0_DATA_WIDTH   32
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE0_DATA_MASK    (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE0_DATA_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_LOCAL_GEN_STORAGE1
 */
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE1    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000434 )
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE1_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE1_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE1_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE1_DATA_SHIFT   0
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE1_DATA_WIDTH   32
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE1_DATA_MASK    (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE1_DATA_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_LOCAL_GEN_STORAGE2
 */
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE2    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000438 )
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE2_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE2_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE2_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE2_DATA_SHIFT   0
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE2_DATA_WIDTH   32
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE2_DATA_MASK    (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE2_DATA_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_LOCAL_GEN_STORAGE3
 */
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE3    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000043C )
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE3_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE3_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE3_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE3_DATA_SHIFT   0
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE3_DATA_WIDTH   32
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE3_DATA_MASK    (u32)0xffffffff
#define PSMX_LOCAL_REG_LOCAL_GEN_STORAGE3_DATA_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE0
 */
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE0    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000440 )
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE0_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE0_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE0_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE0_DATA_SHIFT   0
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE0_DATA_WIDTH   32
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE0_DATA_MASK    (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE0_DATA_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE1
 */
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE1    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000444 )
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE1_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE1_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE1_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE1_DATA_SHIFT   0
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE1_DATA_WIDTH   32
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE1_DATA_MASK    (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE1_DATA_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE2
 */
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE2    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000448 )
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE2_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE2_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE2_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE2_DATA_SHIFT   0
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE2_DATA_WIDTH   32
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE2_DATA_MASK    (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE2_DATA_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE3
 */
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE3    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000044C )
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE3_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE3_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE3_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE3_DATA_SHIFT   0
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE3_DATA_WIDTH   32
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE3_DATA_MASK    (u32)0xffffffff
#define PSMX_LOCAL_REG_PERS_LOC_GEN_STORAGE3_DATA_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_ADDR_ERROR_STATUS
 */
#define PSMX_LOCAL_REG_ADDR_ERROR_STATUS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000450 )
#define PSMX_LOCAL_REG_ADDR_ERROR_STATUS_FULLMASK     (u32)0x00000001
#define PSMX_LOCAL_REG_ADDR_ERROR_STATUS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_ADDR_ERROR_STATUS_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_ADDR_ERROR_STATUS_STATUS_SHIFT   0
#define PSMX_LOCAL_REG_ADDR_ERROR_STATUS_STATUS_WIDTH   1
#define PSMX_LOCAL_REG_ADDR_ERROR_STATUS_STATUS_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_ADDR_ERROR_STATUS_STATUS_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_ADDR_ERROR_INT_MASK
 */
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_MASK    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000454 )
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_MASK_FULLMASK     (u32)0x00000001
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_MASK_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_MASK_DEFVAL   (u32)0x1

#define PSMX_LOCAL_REG_ADDR_ERROR_INT_MASK_MASK_SHIFT   0
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_MASK_MASK_WIDTH   1
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_MASK_MASK_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_MASK_MASK_DEFVAL  (u32)0x1

/**
 * Register: PSMX_LOCAL_REG_ADDR_ERROR_INT_EN
 */
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_EN    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000458 )
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_EN_FULLMASK     (u32)0x00000001
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_EN_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_EN_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_ADDR_ERROR_INT_EN_EN_SHIFT   0
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_EN_EN_WIDTH   1
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_EN_EN_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_EN_EN_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_ADDR_ERROR_INT_DIS
 */
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_DIS    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x0000045C )
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_DIS_FULLMASK     (u32)0x00000001
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_DIS_FULLRWMASK  (u32)0x00000000
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_DIS_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_ADDR_ERROR_INT_DIS_DIS_SHIFT   0
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_DIS_DIS_WIDTH   1
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_DIS_DIS_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_ADDR_ERROR_INT_DIS_DIS_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_PSM_GLOBAL_APB
 */
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000600 )
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_FULLMASK     (u32)0x0000001f
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_FULLRWMASK  (u32)0x00000019
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_DEFVAL   (u32)0x16

#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_RST_N_SHIFT   4
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_RST_N_WIDTH   1
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_RST_N_MASK    (u32)0x00000010
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_RST_N_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLEREQ_SHIFT   3
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLEREQ_WIDTH   1
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLEREQ_MASK    (u32)0x00000008
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLEREQ_DEFVAL  (u32)0x0

#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLEACK_SHIFT   2
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLEACK_WIDTH   1
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLEACK_MASK    (u32)0x00000004
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLEACK_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLE_SHIFT   1
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLE_WIDTH   1
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLE_MASK    (u32)0x00000002
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_POWER_IDLE_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_MAINEXTEN_SHIFT   0
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_MAINEXTEN_WIDTH   1
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_MAINEXTEN_MASK    (u32)0x00000001
#define PSMX_LOCAL_REG_PSM_GLOBAL_APB_MAINEXTEN_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_ECO_1
 */
#define PSMX_LOCAL_REG_ECO_1    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000800 )
#define PSMX_LOCAL_REG_ECO_1_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_ECO_1_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_ECO_1_DEFVAL   (u32)0x0

#define PSMX_LOCAL_REG_ECO_1_VALUE_SHIFT   0
#define PSMX_LOCAL_REG_ECO_1_VALUE_WIDTH   32
#define PSMX_LOCAL_REG_ECO_1_VALUE_MASK    (u32)0xffffffff
#define PSMX_LOCAL_REG_ECO_1_VALUE_DEFVAL  (u32)0x0

/**
 * Register: PSMX_LOCAL_REG_ECO_2
 */
#define PSMX_LOCAL_REG_ECO_2    ( ( PSMX_LOCAL_REG_BASEADDR ) + (u32)0x00000804 )
#define PSMX_LOCAL_REG_ECO_2_FULLMASK     (u32)0xffffffff
#define PSMX_LOCAL_REG_ECO_2_FULLRWMASK  (u32)0xffffffff
#define PSMX_LOCAL_REG_ECO_2_DEFVAL   (u32)0xfc000000

#define PSMX_LOCAL_REG_ECO_2_CPM5_LPD_DFX_SHIFT   31
#define PSMX_LOCAL_REG_ECO_2_CPM5_LPD_DFX_WIDTH   1
#define PSMX_LOCAL_REG_ECO_2_CPM5_LPD_DFX_MASK    (u32)0x80000000
#define PSMX_LOCAL_REG_ECO_2_CPM5_LPD_DFX_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_ECO_2_CPM5_LPD_SHIFT   30
#define PSMX_LOCAL_REG_ECO_2_CPM5_LPD_WIDTH   1
#define PSMX_LOCAL_REG_ECO_2_CPM5_LPD_MASK    (u32)0x40000000
#define PSMX_LOCAL_REG_ECO_2_CPM5_LPD_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_ECO_2_CPM5_GT_DFX_SHIFT   29
#define PSMX_LOCAL_REG_ECO_2_CPM5_GT_DFX_WIDTH   1
#define PSMX_LOCAL_REG_ECO_2_CPM5_GT_DFX_MASK    (u32)0x20000000
#define PSMX_LOCAL_REG_ECO_2_CPM5_GT_DFX_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_ECO_2_CPM5_GT_SHIFT   28
#define PSMX_LOCAL_REG_ECO_2_CPM5_GT_WIDTH   1
#define PSMX_LOCAL_REG_ECO_2_CPM5_GT_MASK    (u32)0x10000000
#define PSMX_LOCAL_REG_ECO_2_CPM5_GT_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_ECO_2_CPM5_PL_DFX_SHIFT   27
#define PSMX_LOCAL_REG_ECO_2_CPM5_PL_DFX_WIDTH   1
#define PSMX_LOCAL_REG_ECO_2_CPM5_PL_DFX_MASK    (u32)0x08000000
#define PSMX_LOCAL_REG_ECO_2_CPM5_PL_DFX_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_ECO_2_CPM5_PL_SHIFT   26
#define PSMX_LOCAL_REG_ECO_2_CPM5_PL_WIDTH   1
#define PSMX_LOCAL_REG_ECO_2_CPM5_PL_MASK    (u32)0x04000000
#define PSMX_LOCAL_REG_ECO_2_CPM5_PL_DEFVAL  (u32)0x1

#define PSMX_LOCAL_REG_ECO_2_VALUE_SHIFT   0
#define PSMX_LOCAL_REG_ECO_2_VALUE_WIDTH   26
#define PSMX_LOCAL_REG_ECO_2_VALUE_MASK    (u32)0x03ffffff
#define PSMX_LOCAL_REG_ECO_2_VALUE_DEFVAL  (u32)0x0

#define PSM_LOCAL_PWR_CTRL_GATES_SHIFT                (0U)
#define PSM_LOCAL_PWR_CTRL_GATES_WIDTH                ((u32)4U)
#define PSM_LOCAL_PWR_CTRL_GATES_MASK                 ((u32)(u32)0x0000000FU)
#define PSM_LOCAL_PWR_CTRL_MAX_PWRUP_STAGES           PSM_LOCAL_PWR_CTRL_GATES_WIDTH
#define PSM_LOCAL_PWR_CTRL_ISO_MASK                   ((u32)(u32)0x00000010U)


#ifdef __cplusplus
}
#endif

#endif /* XPSMFW_PSMX_LOCAL_H_ */
